Conventional complementary metal oxide semiconductor (CMOS) technology is highly effective for lower frequency applications. For higher speed applications that require high transistor switching rates, hole and electron mobility and other physical limitations may lower the extent to which CMOS devices can be utilized. The mobility of electrons traveling through the gate region is influenced greatly by the stress applied. Silicon germanium (SiGe) has been employed as source/drain electrodes for introducing strain into the gate by utilizing a difference in lattice constant between Si and SiGe. Further, with the recent trend of miniaturization, different shapes and configurations of source/drain regions have been attempted, for example using sigma shaped source and drain regions, such as sigma shaped regions with embedded SiGe. In sigma shaped regions the substrate is preferentially etched to form facets on the {111} surface. However, the {111} facets on the Si surface impede growth of embedded SiGe causing non-homogenous and poorly defined SiGe formation in the source/drain regions, which in turn lowers the final stress of embedded SiGe into the gate region.
A need therefore exists for methodology enabling formation of homogenous and well defined embedded SiGe growth within source/drain regions, and the resulting device.